Asic clock floor planning method and structure

ABSTRACT

A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks  110;  positioning a temporary reference insertion point (TIP)  120;  grouping the sinks together with structured clock buffers (SCBs) in a set of levels  140;  and moving the SCBs to improve symmetry of the tree  150.  The SCBs may be of several sizes and may be positioned horizontally  42  or vertically  45  and moved within limits  46  to permit the program to calculate a complete tree.

TECHNICAL FIELD

The field of the invention is that of designing and constructing a clocktree in an integrated circuit.

BACKGROUND ART

In the field of integrated circuits, a constant need is that ofdistributing the clock signal. As clock speeds have increased, thetolerances on clock skew have tightened.

A number of commercial products are on the market to assist in thedesign process. Cadence offers a program, Clock Tree Synthesis (TM),which generates a tree with limits on the size of a buffer and/or on thecomplexity of the floor plan that the tree can accommodate. Synopsisoffers a program, Clock Tree Compiler (TM) that is generally similar.

IBM has a program, using a method described in U.S. Pat. No. 6,204,713,which can handle large buffers, which permits a tree with fewer levels.

The problem in generating clock trees can be described generally asstriking a balance between delay, power consumed and ability toaccommodate circuit blocks that have had their designs frozen. A shortdelay in the clock chain helps control skew. Low power is alwaysdesirable and the ability to reuse predesigned circuit blocks (embeddedprocessors, RAMs, I/O, etc.) without redoing the layout to accommodatethe clock saves greatly on cost in developing an ASIC.

DISCLOSURE OF THE INVENTION

The invention relates to a method of designing a clock tree thataccommodates an existing layout while selecting clock buffer size andorientation to match the floorplan.

Accordingly, a method and corresponding article of manufacture areprovided for designing a clock tree in an integrated circuit comprising:

collecting a set of sink locations 3 in a master list and a set ofblocked areas 47;

(a) selecting a temporary insertion point (TIP) 4, 5;

(b) enclosing the sink 41 at the first level furthest from the TIP in abin 40 that includes a first subset of sinks 43 and remove the firstsubset from the master list;

(c) assigning a first-level structured clock buffer (SCB) 42 to the bin;

repeating steps (a), (b) and (c) above for the remaining sinks in thefirst level of buffers and subsequent levels until the root level isreached;

improving the symmetry of the tree by moving SCB 45 locations withinconstraints 46 to concentrate SCBs in rows and columns;

connecting the root level TIP 610 to lower levels; and

connecting a source (S) of clock signals to the root level TIP.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 lists steps in a preferred embodiment of the invention.

FIG. 2 shows a sample set of sink locations.

FIG. 3 shows an example of grouping the sinks in bins served by abuffer.

FIGS. 4 and 5 show initial and final locations of a set of buffers.

FIG. 6 shows a completed tree.

BEST MODE FOR CARRYING OUT THE INVENTION

The invention is intended to be used in the design of integratedcircuits, especially ASICs, where a short design process is an importantpart of keeping costs down. In the course of designing large-scale(30,000,000+gates) ASICs, the process of routing the clock tree aroundthe pre-designed modules that form the bulk of the ASIC consumes asignificant amount of time and cost.

Among advantages that may arise by application of the invention are thefollowing:

-   -   automatic or manual selection of a reference point (or temporary        insertion point (TIP)) that starts the branching process;    -   flexibility in range and aspect ratio of buffers;    -   choice of either one or both of top-down or bottom-up methods;    -   provision of trees having buffers of different sizes;    -   allowance for the user to intervene in the design;

The sequence of steps according to a preferred embodiment of theinvention is:

collect the clock sink locations and blockage dimensions.

pick the TIP for the lowest (leaf) level

group the sinks in bins, starting with the one furthest from the TIP andplace a first-level buffer in each bin

pick a TIP for the first level

group the first-level buffers in bins, starting with the one furthestfrom the TIP and place a second-level buffer in each bin

repeat the TIP selection and binning step until the root level isreached

improve the symmetry by moving buffers within constraints to concentratebuffers in rows and columns

add buffers from the source to the TIP, and

insert the tree in the netlist.

FIG. 2 illustrates a simplified example of an integrated circuit beingprocessed according to the invention. At the center of the figure,filled rectangle 1 represents the TIP. Hollow rectangles 3 representclock sinks, which is a general term for the interface between the treeand the logic. The logic surrounding the interface points is omitted forclarity in presentation. The diamond on the left side represents thesource of the clock signals. Capital C, 4, represents a point calculatedby taking the mean between the extreme coordinates of all the sinks—e.g.x=(xmax+xmin)/2 and y=(ymax+ymin)/2. The capital C′, 5, represents thecentroid calculated by taking the mean of all the sink coordinates.These sinks will be grouped and assigned to a buffer that distributesthe clock signal.

Buffers according to the invention, referred to as structured clockbuffers (SCBs) are circuits built of N parallel kernels along an axis,where N is greater than or equal to one. These buffers can be invertingor Non-Inverting. Outputs of the kernel are tied together. Balancedwiring is used to wire the circuits of the Structured Clock Buffers.U.S. Pat. No. 6,204,713, incorporated by reference, explains the designand construction of such buffers.

It is an advantageous feature of the invention that the buffers are notrestricted to a layout along a single axis (horizontal or vertical) butthat layout along both axes may be provided, in order to permit a bufferto fit in a limited space. As those skilled in the art are aware,circuit layout is conventionally done with the axis of the transistorslined with one of the coordinate directions.

Designing a vertical buffer that fits within a layout that was intendedto be horizontal is non-trivial and requires that the transistors in thevertical SCBs must be in same orientation as the horizontal SCBs. Inaddition, balanced wiring is needed for both orientations. Power ringsare needed for either the vertical or horizontal SCB to account fordifferences in the vertical or horizontal power distribution. This mayrequire an additional wiring level for vertical or horizontal SCBs inorder to fit in additional wires. Layouts are modified so that eachhorizontal SCB has a delay and output drive capability that match acorresponding vertical SCB.

The TIP can be calculated automatically by calculating the delay, powerand placability at the center of the sinks (C), the centroid of thesinks (C′) and at a set of intermediate points between C and C′. Theselection rule is summarized as: If the center of the sinks is closer tothe source than the centroid is, then the TIP is placed at the center.If there is a block (a module that cannot be re-drawn) at the center,then the TIP is placed at a different location, either the centroid orat one of the intermediate points between the center and the centroid.

The placability algorithm produces a result of zero if the location isblocked. The best score is generated by an unblocked location largeenough for the SCB, and closest to the desired placement point. Thescore decreases as the distance from the desired point increases,reflecting the undesirability of additional distance.

The TIP point can be determined by calculating a score that is the sumS1W1+S2W2+S3W3, where S1, S2 and S3 are 0 or 1, depending on whichaspect the designer wishes to emphasize and W1=K1*Delay, W2=K2*Power andW3=K3*Placability, where Ki is determined empirically

Once the TIP has been placed, the sinks at the lowest level of the clocktree are grouped. A rectangle (bin) is placed, just enclosing the sinkfarthest from the TIP. The initial size of the bin is set empirically,based on experience with the density of sinks. The bin may be adjustedup or down to approach the desired size. Illustratively, a bin holdingabout 20 The actual number is determined by the drive capability of theSCB and the wiring delays to get to the sinks.

Similarly, the number of levels in the tree will be set empirically,e.g. at three. Again the actual number is determined by the drivecapability of the SCB and the wiring delay's to get to the sinks. Morelevels can be added for larger trees.

A buffer is placed at the center of the rectangle, which may be movedslightly in the x and/or y directions to accommodate the maximum numberof sinks. The size of the buffer is set to be able to drive the sinks inthe bin. It is an advantageous feature of the invention that the size ofthe buffers may be selected from a set of pre-designed buffers in orderto drive the number of sinks that happen to be in the bin, rather thancutting down the size of the bin to accommodate the buffer. The sinksincluded in that bin are deleted from the master list of sinks and thenext bin is placed.

FIG. 3 has been drawn to illustrate a situation in which a pair ofmodules 45 and 47 are located such that a horizontal buffer will notfit. According to the invention, the buffer is moved toward the TIP totry to find a location that fits and still permits the buffer to drivethe sinks. If such a location is not found, a vertical buffer is placed.If a vertical buffer will not fit, the program places a horizontalbuffer in the original location, even if it is overlapping fixed blocks,printing a warning message for the user to correct it manually. Such asituation is illustrated with buffer 42. The sequence is that theprogram will exhaust the possibilities in the horizontal, and thenexhaust the possibilities in the vertical then warn the user if noplacement is possible.

Referring now to FIG. 3, there is shown a set of three SCB areasrepresented by boxes 20, 30 and 40 holding sink subsets 23, 33 and 43and positioned around SCBs 22, 32 and 42, respectively. The dimensionsof a box represent the distance over which a clock signal can betransmitted by the SCB at the center of the box within the restrictionson skew, etc. set by the circuit designer. Illustratively, the boxeshave been shifted to have a boundary that is next to the extremeposition of a sink—i.e. box 20 has been placed so that the sink 21,furthest from the TIP is at its edge; similarly for box 30 and sink 31and for box 40 and sink 41.

According to the invention, the size of the SCB will be set to drive thesinks within its range. It is an advantageous feature of the inventionthat the size of a buffer is flexible.

Once the first bin is set, the sink remaining in the master list that isfurthest from the TIP is located and a bin is placed enclosing it. Thepreceding procedure is repeated until all the sinks have been placed inbins. This covers the leaf level of the clock tree.

The binning procedure is repeated, using first and second level buffersin place of leaf-level sinks, until the root level of the tree isreached.

Once the sinks have been allocated to SCBs, a process of improving thesymmetry of the tree can be performed. FIG. 4 shows a simplified exampleof a layout in which three SCBs 142, have been fixed for one reason oranother and will not be moved in this step. Examples of a fixed SCB maybe a customer pre-placing and assigning one SCB to some high speedcritical circuits (i.e. high speed interface). Another case might be onewhere part of the chip already meets the timing requirements and thecustomer does not wish to revisit the compromises made to get thatresult.

Blocks 47 represent layout modules that will not be moved. The clocktree must be routed around them. The other SCBs, labeled 45, can bemoved. In this example, there is a 10×10 grid and a rule that an SCB canbe moved by only one step vertically or horizontally. Possible moves areindicated by the arrows.

The principle of the move is to concentrate SCBs on the same row orcolumn, thereby providing a more compact distribution net andsimplifying skew and latency.

The procedure followed is to calculate, for each row and column, thenumber of SCBs in that row or column, and the number that could beincluded within the rules. The numbers on the side and bottom indicatethe actual number and potential number of SCBs in that row or column.

FIG. 5 shows the final configuration of SCBs after allowed moves havebeen made. The effect of the moves has been to concentrate thehorizontal distribution in four rows, with the vertical distributionbeing spread more broadly.

FIG. 6 shows the result of connecting the SCBs from FIG. 5. Leaf-levelbuffers are denoted with numeral 630. Second-level buffers are denotedwith numeral 620 (located in the middle, about one third from the bottomand from the top). The root level buffer is denoted with numeral 610,located at the center. Location of the root at or near the center is notrequired, though it contributes to symmetry and a compact layout. Thelocation of the source is not shown in this Figure. It will be locatedat a fixed position and a route constructed from it to SCB 610.

The temporary insertion point, which is used in each level of the clocktree looks at both its sink circuits (bottom of tree) and the sourcecircuit for those sinks (top of tree).

While the invention has been described in terms of a single preferredembodiment, those skilled in the art will recognize that the inventioncan be practiced in various versions within the spirit and scope of thefollowing claims.

INDUSTRIAL APPLICABILITY

The invention has applicability to the design and fabrication ofintegrated electronic circuits.

1. A method of designing a clock tree in an integrated circuitcomprising the steps of: collecting a set of sink locations 3 in amaster list and a set of blocked areas 47; (a) selecting a temporaryinsertion point (TIP) 4, 5; (b) enclosing the sink 41 at the first levelfurthest from the TIP in a bin 40 that includes a first subset of sinks43 and remove the first subset from the master list; p1 (c) assigning afirst-level structured clock buffer (SCB) 42 to the bin; repeating steps(a), (b) and (c) above for the remaining sinks in the first level ofbuffers and subsequent levels until the root level is reached; improvingthe symmetry of the tree by moving SCB 45 locations within constraints46 to concentrate SCBs in rows and columns; connecting the root levelTIP 610 to lower levels; and connecting a source (S) of clock signals tothe root level TIP.
 2. A method according to claim 1, in which said step(a) of selecting a TIP (4,5) comprises calculating a center 4 of sinksand a centroid 5 of sinks and automatically placing said TIP at one ofsaid center, centroid or an intermediate point between said center andcentroid in accordance with an algorithm that locates available space.3. A method according to claim 2, in which said step (a) of selecting aTIP (4,5) comprises calculating a center 4 of sinks and a centroid 5 ofsinks and automatically placing said TIP at one of said center 4,centroid 5 or an intermediate point between said center and centroid inaccordance with an algorithm that locates selectively weights one ormore of delay, power consumed and placability.
 4. A method according toclaim 1, in which said step (c) of assigning a first-level SCB 42 to thebin comprises steps of attempting to place a horizontal SCB 42, thenattempting to place a vertical SCB 42 in a central location when ahorizontal SCB will not fit in said central location.
 5. A methodaccording to claim 4, in which said vertical SCB comprises a set ofcircuit elements laid out to have substantially the same delay as acorresponding SCB with horizontal layout.
 6. A method according to claim1, in which said step of improving symmetry comprises a step ofcalculating for each of a set of columns and rows a potentialimprovement in symmetry of SCBs 45 in an nth level of said tree andmoving SCBs 45 to improve symmetry.
 7. A method according to claim 6, inwhich some designated SCBs 142 are excluded from the calculation in saidstep of improving symmetry, whereby only a subset 45 of SCBs areincluded in the calculation.
 8. A method according to claim 6, in whichthe amount of movement permitted to improve symmetry 46 is restricted toa preset amount.
 9. A method according to claim 1, in which said SCB 42assigned to a subset of sinks is selected from a set of predesigned SCBsof varying capacity.
 10. An article of manufacture in computer readableform which encodes a set of instructions for performing a methodaccording to claim 1.